1. Technical Field of the Invention
The present invention relates to differential amplifier circuits and, more specifically, to stabilizing the output common mode voltage of such differential amplifier circuits over a large common mode input range.
2. Description of Related Art
Reference is now made to FIG. 1 which illustrates a schematic diagram of a prior art differential amplifier 10 with large bandwidth and fixed controlled gain. Such an amplifier is often used as a pre-amplifier. The differential amplifier 10 includes an input stage comprising a pair of PMOS input transistors 12 and 14. The gate of transistor 12 receives an input signal INP while the gate of transistor 14 receives an input signal INN. The input signals INP and INN form a differential input signal. The sources of input transistors 12 and 14 are connected together at node 16. The input stage further includes a PMOS tail current source transistor 18 for the differential input transistors 12 and 14 that is connected between a positive supply node (VDD) and node 16. A bias voltage Vbias is applied to the gate of transistor 18. The source of transistor 18 is coupled to receive power from the positive supply node (VDD).
The differential amplifier 10 further includes a pair of NMOS transistors 20 and 22 (cascode devices). The gates of transistors 20 and 22 are connected together and further receive a bias voltage VCN. The source of transistor 20 is connected to the drain of transistor 12 at node 24, and the source of transistor 22 is connected to the drain of transistor 14 at node 26. This forms the well recognized folded cascode amplifier architecture. A first resistance (for example, a resistor) 28 is connected between node 24 and a ground node (GND), while a second resistance (for example, a resistor) 30 is connected between node 26 and the ground node (GND).
A first output signal OUTN for the amplifier 10 is taken at the drain of transistor 20 (node 32). A second output signal OUTP for the amplifier 10 is taken at the drain of transistor 22 (node 34). The output signals OUTN and OUTP form a differential output signal. A third resistance (for example, a resistor) 36 is connected between node 32 and the positive supply node (VDD), while a fourth resistance (for example, a resistor) 38 is connected between node 34 and the positive supply node (VDD).
Under balanced conditions, IS=(IT/2)+IL; where IS is the current in resistance 28 or 30, and IL is the load current in resistance 36 or 38. The common mode voltage at the output is Vcm=VDD−R28*IL=VDD−(2*IS−IT); where R28 is the value of the resistance 28. As the common mode input voltage (V(INP)+V(INN))/2 increases towards VDD, the tail current IT decreases due to the limited output impedance of the PMOS tail current transistor 18. This decrease is even greater in instances of a low voltage VDD where it is not possible to cascode on transistor 18. As the tail current IT decreases, the common mode voltage at the output (Vcm) decreases in the manner generally shown with line 100 of FIG. 4 (this is caused because the load current IL correspondingly increases due to the fact that VCN is a constant bias to the gate, and thus the voltage at nodes 24 and 26 decreases, resulting in an increasing gate-source voltage for the cascode transistors 20 and 22). The relationship between common mode voltage at the input and common mode voltage at the output exhibits a very large slope (for example, a 20% change has been observed in simulating the operation of FIG. 1 for a given process technology). This decrease in common mode voltage at the output as common mode voltage at the input increases can cause trouble for following circuits (for example, latches in high speed links) coupled to the output nodes 32 and 34. A need exists to keep the output common mode voltage as fixed or steady (i.e., stabilized) as possible responsive to changes in the input common mode voltage.
It will be noted that the foregoing concern exists as well when the differential amplifier instead uses an NMOS input stage (as opposed to the PMOS input stage of FIG. 1). The problem also exists for combined PMOS and NMOS input stages configured for widening the common mode input range.
Reference is now made to FIG. 2 which illustrates a schematic diagram of a prior art differential amplifier 50. The amplifier 50 has a circuit configuration similar to that of amplifier 10 in FIG. 1. Thus, like reference numbers are used for like components and connections. To address the issues noted above, the amplifier 50 includes a resistive divider circuit 52 for sensing the common mode output voltage. The resistive divider circuit 52 is connected across the output nodes 32 and 34. The circuit 52 could alternatively be implemented using gate isolated structures as known in the art. This circuit 52 undesirably adds a current load (resistive or capacitive) onto the output of the amplifier 50. The voltage at the tap node 54 is compared by a first comparison amplifier 56 to a fixed common mode reference voltage (VCMref). The output of the first comparison amplifier 56 is applied to the gate of an added tail current source transistor 58 connected in parallel with the tail current source transistor 18. The feedback provided by amplifier 56 and transistor 58 alters the tail current IL of the amplifier 50 responsive to the sensed common mode output voltage so as to stabilize the common mode voltage level. However, both transistor 18 and transistor 58 suffer from limited output impedance so that the tail current source may enter the linear operating region due to operation of the negative feedback loop resulting in loss of loop control as the input common mode voltage increases. Moreover, the loading of the output nodes 32 and 34 (either resistively as shown with circuit 52, or capacitively in the case of the use of gate isolated structures) is not preferred when amplifier 50 must operate as a high speed amplifier.
An alternative implementation, also shown in FIG. 2, uses a second comparison amplifier 60 to compare the voltage at the tap node 54 to the fixed common mode reference voltage (VCMref). The output of the second comparison amplifier 60 is applied as the bias voltage VCN to the connected gates of the pair of NMOS transistors 20 and 22. While this solution does not suffer from the potential problem of losing loop control, it does share the concern regarding output loading due to the sensing of the output common mode voltage level with circuit 52.
U.S. Pat. No. 7,532,072 (the disclosure of which is hereby incorporated by reference) provides another solution, but the disclosed solution, like the circuit of FIG. 2, suffers from the same concerns over losing loop control and output loading.
A need exists in the art for a differential amplifier circuit having a stabilized output common mode voltage over large common mode input ranges without loading the outputs of the amplifier for use in high speed applications.